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ltc3619b 3619bfa typical a pplica t ion descrip t ion 400ma/800ma synchronous step-down dc/dc with average input current limit the ltc ? 3619b is a dual monolithic synchronous buck regulator using a constant frequency current mode ar- chitecture. the input supply voltage range is 2.5v to 5.5v, making it ideal for li-ion and usb powered applications. 100% duty cycle capability provides low dropout operation, extend- ing the run time in battery-operated systems. low output voltages are supported with the 0.6v feedback reference voltage. channel 1 and channel 2 can supply 400ma and 800ma output current, respectively. the ltc3619bs programmable average input current limit is ideal for usb applications and for point-of-load power supplies because the ltc3619bs limited input current will still allow its output to deliver high peak load currents without collapsing the input supply. when the sum of both channels currents exceeds the input current limit, channel 2 is current limited while channel 1 remains regu- lated. the operating frequency is internally set at 2.25mhz allowing the use of small surface mount inductors. internal soft-start reduces in-rush current during start-up. the ltc3619b is available in small msop and 3mm 3mm dfn packages. the ltc3619b is also available in a low quiescent current, high effciency burst mode ? version, ltc3619. dual monolithic buck regulator in 10-lead 3mm 3mm dfn fea t ures a pplica t ions n programmable average input current limit: 5% accuracy n dual step-down outputs: up to 96% effciency n low noise pulse-skipping operation at light loads n input voltage range: 2.5v to 5.5v n output voltage range: 0.6v to 5v n 2.25mhz constant-frequency operation n power good output voltage monitor for each channel n low dropout operation: 100% duty cycle n independent internal soft-start for each channel n current mode operation for excellent line and load transient response n 2% output voltage accuracy n short-circuit protected n shutdown current 1a n available in small thermally enhanced 10-lead ms and 3mm 3mm dfn packages n high peak load current applications n usb powered devices n supercapacitor charging n radio transmitters and other handheld devices gsm pulse load v in run2 run1 ltc3619b v fb2 sw2 sw1 pgood1 pgood2 v fb1 22pf rlim gnd v in 3.4v to 5.5v v out2 3.4v at 800ma v out1 1.8v at 400ma 3619b ta01 1190k 511k 255k 255k 1.5h 3.3h 2.2mf s2 supercap 10f 10f + 1000pf 116k i lim = 475ma l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s.patents, including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131. 1ms/div v in = 5v, 500ma compliant i load = 0a to 2.2a, channel 1 unloaded 3619b ta01b v out 200mv/div i out 500ma/div i in 500ma/div v in ac-coupled 1v/div
ltc3619b 3619bfa a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ............................. C0.3 to 6v v fb1 , v fb2 ........................................ C0.3v to v in + 0.3v run1, run2, rlim .......................... C0.3v to v in + 0.3v sw1, sw2 ........................................ C0.3v to v in + 0.3v pgood1, pgood2 ........................... C0.3v to v in + 0.3v p-channel sw source current (dc) (note 2) channel 1 ........................................................ 600ma channel 2 ................................................................1a n-channel sw source current (dc) (note 2) channel 1 ........................................................ 600ma channel 2 ................................................................1a (note 1) top view dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v fb2 run2 pgood2 sw2 v in v fb1 run1 rlim pgood1 sw1 11 gnd t jmax = 125c, ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 v fb1 run1 rlim pgood1 sw1 10 9 8 7 6 v fb2 run2 pgood2 sw2 v in top view mse package 10-lead plastic msop 11 gnd t jmax = 125c, ja = 45c/w exposed pad (pin 11) is gnd, must be soldered to pcb p in c on f igura t ion symbol parameter conditions min typ max units v in v in operating voltage range l 2.5 5.5 v v uv v in undervoltage lockout v in low to high l 2.1 2.5 v o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3619bedd#pbf ltc3619bedd#trpbf lffh 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3619bidd#pbf ltc3619bidd#trpbf lffh 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3619bemse#pbf ltc3619bemse#trpbf ltffj 10-lead plastic msop C40c to 125c ltc3619bimse#pbf ltc3619bimse#trpbf ltffj 10-lead plastic msop C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ peak sw source and sink current (note 2) channel 1 ........................................................ 900ma channel 2 ............................................................. 2.7a operating junction temperature range (notes 3, 6, 8) ........................................C40 to 125c storage temperature range .................. C65c to 125c lead temperature (soldering, 10 sec) msop package ................................................. 300c refow peak body temperature ............................ 260c e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c (note 3)
ltc3619b 3619bfa e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by long term current density limitations. note 3: the ltc3619b is tested under pulsed load conditions such that t j t a . the ltc3619be is guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3619bi is guaranteed to meet specifed performance over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t a = 25c (note 3) note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: the switch on-resistance is guaranteed by correlation to wafer level measurements. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 7: the converter is tested in a proprietary test mode that connects the output of the error amplifer to the sw pin, which is connected to an external servo loop. note 8: t j is calculated from the ambient temperature t a and the power dissipation as follows: t j = t a + (p d )( ja c/w) symbol parameter conditions min typ max units i fb feedback pin input current l 30 na v fbreg feedback voltage (channels 1, 2) ltc3619be, C40c < t j < 85c (note 7) ltc3619bi, C40c < t j < 125c (note 7) l l 0.588 0.582 0.600 0.600 0.612 0.618 v v v linereg v fb line regulation v in = 2.5v to 5.5v (note 7) 0.01 0.25 %/v v loadreg v fb load regulation (channel 1) v fb load regulation (channel 2) i load = 0ma to 400ma (note 7) i load = 0ma to 800ma (note 7) 0.5 0.5 % % i s supply current active mode (note 4) shutdown v fb1 = v fb2 = 0.95 v fbreg v run1 = v run2 = 0v, v in = 5.5v 600 875 1 a a f osc oscillator frequency v fb = v fbreg l 1.8 2.25 2.7 mhz i lim(peak) peak switch current limit channel 1 (400ma) channel 2 (800ma) v in = 5v, v fb < v fbreg , duty cycle <35% 550 1800 800 2400 ma ma i inlim input average current limit rlim = 116k rlim = 116k, ltc3619be rlim = 116k, ltc3619bi l l 450 437 427 475 475 475 500 513 523 ma ma ma r ds(on) channel 1 (note 5) top switch on-resistance bottom switch on-resistance channel 2 (note 5) t op switch on-resistance bottom switch on-resistance v in = 5v, i sw = 100ma v in = 5v, i sw = 100ma v in = 5v, i sw = 100ma v in = 5v, i sw = 100ma 0.45 0.35 0.27 0.25 i sw(lkg) switch leakage current v in = 5v, v run = 0v 0.01 1 a t softstart soft-start time v fb from 0.06v to 0.54v 0.3 0.95 1.3 ms v run run threshold high l 0.4 1 1.2 v i run run leakage current 0v v run 5v l 0.01 1 a pgood power good threshold entering window v fb ramping up v fb ramping down leaving window v fb ramping up v fb ramping down C5 5 C7 7 9 C9 11 C11 % % % % pgood blanking power good blanking time pgood rising and falling, v in = 5v 90 s r pgood power good pull-down on-resistance 8 15 30 i pgood pgood leakage current v pgood = 5v 1 a
ltc3619b 3619bfa typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5v, unless otherwise noted. switch leakage vs input voltage pulse-skipping mode operation effciency vs input voltage regulated voltage vs temperature oscillator frequency vs temperature supply current vs temperature switch on-resistance vs input voltage switch on-resistance vs temperature, channel 1 v in = 5v v out = 3.3v i load = 5ma 3619b g01 sw 2v/div i l 100ma/div v out 50mv/div ac- coupled 5s/div v in (v) v out = 3.3v channel 2 3.5 efficiency (%) 100 90 40 20 50 60 70 80 30 10 0 4.5 3619b g03 5.5 4 5 i out = 10ma i out = 1ma i out = 0.1ma i out = 100ma i out = 400ma i out = 800ma temperature (c) ?50 v fb error (%) 1.5 1.0 ?1.0 ?0.5 0 0.5 ?1.5 7550250 3619b g04 125 ?25 100 temperature (c) ?50 frequency (mhz) 2.5 2.4 1.9 2.0 2.2 2.1 2.3 1.8 7550250 3619b g05 125 ?25 100 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5v temperature (c) ?50 supply current (a) 900 800 300 400 600 500 700 200 7550250 3619b g02 125 ?25 100 v in = 2.7v v in = 5.5v run1 = run2 = v in i load = 0a v in (v) 2.5 leakage current (pa) 1000 800 400 200 600 0 54.543.5 3619b g06 5.5 3 main switch synchronous switch channel 1 channel 2 v in (v) 2.5 r ds(on) (m) 650 550 350 450 250 54.543.5 3619b g07 5.5 3 main switch synchronous switch channel 1 channel 2 temperature (c) ?50 ?25 r ds(on) () 0.7 0.6 0.4 0.3 0.5 0.2 100755025 3619b g08 125 0 main switch synchronous switch v in = 2.7v v in = 3.6v v in = 5v temperature (c) ?50 ?25 pfet r ds(on) () nfet r ds(on) () 0.5 0.4 0.2 0.1 0 0.3 ?0.1 0.7 0.6 0.4 0.3 0.2 0.5 0.1 100755025 3619b g09 125 0 main switch synchronous switch v in = 2.7v v in = 3.6v v in = 5v switch on-resistance vs temperature, channel 2
ltc3619b 3619bfa typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5v, unless otherwise noted. effciency vs load current effciency vs load current effciency vs load current effciency vs load current load regulation load regulation line regulation start-up from shutdown start-up from shutdown output current (a) efficiency (%) 3619b g10 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.1 1 0.01 0.001 v out = 3.3v channel 1 v in = 3.6v v in = 4.2v v in = 5v output current (a) efficiency (%) 3619b g11 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.1 1 0.01 0.001 v out = 3.3v channel 2 v in = 3.6v v in = 4.2v v in = 5v output current (a) efficiency (%) 3619b g12 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.1 1 0.01 0.001 v out = 1.2v channel 1 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5v output current (a) efficiency (%) 3619b g13 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.1 1 0.01 0.001 v out = 1.2v channel 2 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5v load current (ma) v out error (%) 3619b g14 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 0 300 400 200 100 channel 1 v out = 1.8v v out = 2.5v v out = 3.3v load current (ma) v out error (%) 3619b g15 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 0 300 400 500 600 700 800 200100 channel 2 v out = 1.8v v out = 2.5v v out = 3.3v v in (v) v out error (%) 3619b g16 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v out = 1.8v i load = 100ma v in = 5v, v out = 3.3v r load = 7 c load = 4.7f 3619b g17 run 2v/div i l 250ma/div v out 1v/div 200s/div v in = 5v, v out = 3.4v r l = no load, c l = 4.4mf c lim = 2200pf, i lim = 500ma 3619b g18 run 2v/div i in 500ma/div v out 2v/div r lim 1v/div 2ms/div channel 2
ltc3619b 3619bfa v fb1 (pin 1/pin 1): regulator 1 output feedback. receives the feedback voltage from the external resistive divider across the regulator 1 output. nominal voltage for this pin is 0.6v. run1 (pin 2/pin 2): regulator 1 enable. forcing this pin to v in enables regulator 1, while forcing it to gnd causes regulator 1 to shut down. rlim (pin 3/pin 3): average input current limit program pin. place a resistor and capacitor in parallel from this pin to ground. pgood1 (pin 4/pin 4): open-drain logic output. pgood1 is pulled to ground if the voltage on the v fb1 pin is not within power good threshold. sw1 (pin 5/pin 5): regulator 1 switch node connection to the inductor. this pin swings from v in to gnd. v in (pin 6/pin 6): main power supply. must be closely de-coupled to gnd. sw2 (pin 7/pin 7): regulator 2 switch node connection to the inductor. this pin swings from v in to gnd. pgood2 (pin 8/pin 8): open-drain logic output. pgood2 is pulled to ground if the voltage on the v fb2 pin is not within power good threshold. run2 (pin 9/pin 9): regulator 2 enable. forcing this pin to v in enables regulator 2, while forcing it to gnd causes regulator 2 to shut down. v fb2 (pin 10/pin 10): regulator 2 output feedback. receives the feedback voltage from the external resistive divider across the regulator 2 output. nominal voltage for this pin is 0.6v. gnd (pin 11/pin 11): ground. bottom exposed pad. con- nect to the (C) terminal of c out , and the (C) terminal of c in . the exposed pad must be soldered to pcb. p in func t ions typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5v, unless otherwise noted. (dd/mse) average input current limit vs temperature load step load step temperature (c) ?50 ?8 i inlim error (%) ?4 ?2 ?6 0 6 4 2 8 75 100 50250?25 3619b g19 125 v in = 5v i lim = 475ma v in = 5v, v out = 3.3v i load = 0a to 400ma c l = 4.7f 20s/div 3619b g20 i load 500ma/div i l 500ma/div v out 200mv/div ac-coupled v in = 5v, v out = 1.8v i load = 40ma to 400ma c l = 4.7f 20s/div 3619b g21 i load 500ma/div i l 500ma/div v out 200mv/div ac-coupled
ltc3619b 3619bfa func t ional diagra m ? + ? + ea ? + v sleep i th switching logic and blanking circuit s r q q rs latch ? + i comp i rcmp anti shoot- thru slope comp sleep 0.6v ref osc osc regulator 2 sleep1 sleep2 shutdown regulator 1 sw1 3619b fd 10 2 9 run1 run2 v fb1 8 pgood1 7 v in 6 gnd 11 rlim 3 0.6v min clamp soft-start v fb1 0.546v 0.654v + ? 1v to regulator 2 only + ? + ? ? ? + ? + ea ? + v sleep i th switching logic and blanking circuit s r q q rs latch ? + i comp i rcmp anti shoot- thru slope comp sleep shutdown sw2 1 v fb2 4 pgood2 5 v in 6 gnd 11 0.6v min clamp soft-start v fb2 0.546v 0.654v + ? + ? ? + i comp ? + i comp
ltc3619b 3619bfa o pera t ion the ltc3619b uses a constant-frequency, current mode architecture. the operating frequency is set at 2.25mhz. both channels share the same clock and run in-phase. the output voltage is set by an external resistor divider returned to the v fb pins. an error amplifer compares the divided output voltage with a reference voltage of 0.6v and regulates the peak inductor current accordingly. the ltc3619b continuously monitors the input current of both channels. when the sum of the currents of both channels exceeds the programmed input current limit set by an external resistor, r lim , channel 2 is current limited while channel 1 remains regulated. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the reference voltage. the current into the inductor and the load increases until the peak inductor current (controlled by i th ) is reached. the rs latch turns off the synchronous switch and energy stored in the inductor is discharged through the bottom switch (n-channel mosfet) into the load until the next clock cycle begins, or until the inductor current begins to reverse (sensed by the i rcmp comparator). the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the er- ror amplifer. this amplifer regulates the v fb pin to the internal 0.6v reference by adjusting the peak inductor current accordingly. when the input current limit is engaged, the peak inductor current will be lowered, which then reduces the switching duty cycle and v out . this allows the input voltage to stay regulated when its programmed current output capability is met. light load operation the ltc3619b will automatically transition from continuous operation to the pulse-skipping operation when the load current is low. the inductor current is not fxed during the pulse-skipping mode which allows the ltc3619b to switch at constant-frequency down to very low currents, where it will begin skipping pulses to maintain output regulation. this mode of operation exhibits low output ripple as well as low audio noise and reduced rf interference while providing reasonable low current effciency. dropout operation when the input supply voltage decreases toward the output voltage the duty cycle increases to 100%, which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of the p-channel switch increases with decreasing input supply voltage (see the typical performance characteristics sec- tion). therefore, the user should calculate the worst-case power dissipation when the ltc3619b is used at 100% duty cycle with low input voltage (see thermal considerations in the applications information section). soft-start in order to minimize the inrush current on the input bypass capacitor, the ltc3619b slowly ramps up the output volt- age during start-up. whenever the run1 or run2 pin is pulled high, the corresponding output will ramp from zero to full-scale over a time period of approximately 750s. this prevents the ltc3619b from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. when the output is loaded heavily, for example, with mil- lifarad of capacitance, it may take longer than 750s to charge the output to regulation. if the output is still low after the soft-start time, the ltc3619b will try to quickly charge the output capacitor. in this case, the input current limit (after it engages) can prevent excessive amount of instantaneous current that is required to quickly charge the output. see the channel 2 start-up from shutdown curve in the typical performance characteristics section. after input current limit is engaged, the output slowly ramps up to regulation while limited by its 500ma of input current.
ltc3619b 3619bfa o pera t ion short-circuit protection when either regulator output is shorted to ground, the corresponding internal n-channel switch is forced on for a longer time period for each cycle in order to allow the inductor to discharge, thus preventing inductor current runaway. this technique has the effect of decreasing switching frequency. once the short is removed, normal operation resumes and the regulator output will return to its nominal voltage. input current limit internal current sense circuitry in each channel measures the inductor current through the voltage drop across the power pfet switch and forces the same voltage across the small sense pfet. the voltage across the small sense pfet generates a current representing 1/55,000th of the inductor current during the on-cycle. the current out of rlim pin is the summed representation of the inductor currents from both channels, which can be expressed in the following equation. i rlim = i out1 ? d1 ? k1 + i out2 ? d2 ? k2, where d1 = v out1 /v in and d2 = v out2 /v in are the duty cycle of channel 1 and 2, respectively. k1 is the ratio r ds(on) (power pfet)/r ds(on) (sense pfet) of channel 1, and k2 is the ratio r ds(on) (power pfet)/ r ds(on) (sense pfet) of channel 2. the ratio of the power pfet to the sense pfet is trimmed to within 2%. given that both pfets are carefully laid out and matched, their temperature and voltage coeffcient effects will be similar and their terms be canceled out in the equation. in that case, the constants k1 and k2 will only be dependent on area scaling, which is trimmed to within 2%. thus, the i rlim current will track the input current very well over varying temperature and v in . the rlim pin can be grounded to disable input current limit function. programming input current limit selection of one external r lim resistor will program the input current limit. the current limit can be programmed from 200ma up to i peak current. as the input current increases, r lim voltage will follow. when r lim reaches the internal comparator threshold of 1v, channel 2s power pfet on-time will be shortened, thereby, limiting the input current. use the following equation to select the r lim resistance that corresponds to the input current limit. r k a i a lim dc = ? 55 ? ( ) i dc is the input current (at v in ) to be limited. the follow- ing are some r lim values with the corresponding current limit. r lim i dc 91.6k 600ma 110k 500ma 137.5k 400ma selection of c lim capacitance since i rlim current is a function of the inductor current, its dependency on the duty cycle cannot be ignored. thus, a c lim capacitor is needed to integrate the i rlim current and smooth out transient currents. the ltc3619b is stable with any size capacitance >100pf at the rlim pin. each application input current limit will call for different c lim value to optimize its response time. using a large c lim capacitor requires longer time for the rlim pin voltage to charge. for example, consider the application 500ma input current limit, 5v input and 1a, 2.5v output with a 50% duty cycle. when an instantaneous 1a output pulse is applied, the current out of the rlim pin becomes 1a/55k = 18.2a during the 50% on-time or 9.1a full duty cycle. with a c lim capacitor of 1f, r lim of 116k, and using i = cdv/dt, it will take 110ms for c lim to charge from 0v to 1v. this is the time after which the ltc3619b will start input current
ltc3619b 0 3619bfa limiting. any current within this time must be considered in each application to determine if it is tolerable. figure 1a shows v in (i in ) current below input current limit with a c lim capacitor of 0.1f. channel 1 is unloaded to simplify calculations. when the load pulse is applied, under the specifed condition, i lim current is 1.1a/55k ? 0.66 = 13.2a, where 0.66 is the duty cycle. it will take a little more than 7.5ms to charge the c lim capacitor from 0v to 1v, after which the ltc3619b begins to limit input current. the i in current is not limited during this 7.5ms time and is more than 725ma. this current transient may cause the input supply to temporarily droop if the supply current compliance is exceeded, but recovers after the input current limit engages. the output will continue to deliver the required current load while the output voltage droops to allow the input voltage to remain regulated during input current limit. for applications with short load pulse duration, a smaller c lim capacitor may be the better choice as in the example shown in figure 1b. channel 1 is unloaded for simplif- cation. in this example, a 577s, 0a to 2a output pulse is applied once every 4.7ms. a c lim capacitor of 2.2nf requires 92s for v rlim to charge from 0v to 1v. during this 92s, the input current limit is not yet engaged and the output must deliver the required current load. this may cause the input voltage to droop if the current com- pliance is exceeded. depending on how long this time is, the v in supply decoupling capacitor can provide some of this current before v in droops too much. in applications with a bigger v in supply decoupling capacitor and where v in supply is allow to droop closer to dropout, the c lim capacitor can be increased slightly. this will delay the start of input current limit and artifcially regulated v out before input current limit is engaged. in this case, within the 577s load pulse, the v out voltage will stay artifcially regulated for 92s out of the total 577s before the input current limit activates. this approach may be used if a faster recovery on the output is desired. selecting a very small c lim will speed up response time but it can put the device within threshold of interfering with normal operation and input current limit in every few switching cycles. this may be undesirable in terms of noise. use 2rc >> 100/clock frequency (2.25mhz) as o pera t ion figure 1a. input current limit within 100ms load pulses 50ms/div v in = 5v, 500ma compliant r lim = 116k, c lim = 0.1f i load = 0a to 1.1a, c out = 2.2mf, v out = 3.3v i lim = 475ma, channel 1 not loaded 3619b f01a v out 2v/div v rlim 1v/div i l 1a/div i in 500ma/div 1ms/div v in = 5v, 500ma compliant r lim = 116k, c lim = 2200pf i load = 0a to 2a, c out = 2.2mf, v out = 3.3v i lim = 475ma, channel 1 not loaded 3619b f01b v out 200mv/div i out 500ma/div i in 500ma/div v in ac-coupled 1v/div figure 1b. input current limit within 577s, 2a repeating load pulses
ltc3619b 3619bfa a general ltc3619b application circuit is shown in figure 2. external component selection is driven by the load require- ment, and begins with the selection of the inductor l. once the inductor is chosen, c in and c out can be selected. inductor selection although the inductor does not infuence the operat- ing frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : i l = v out f o ? l ? 1 ? v out v in ? ? ? ? ? ? (1) accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is 40% of the maximum output load current. so, for a 800ma regulator, i l = 320ma (40% of 800ma). the inductor value will also have an effect on burst mode operation. the transition to low current operation begins when the peak inductor current falls below a level set by the internal burst clamp. lower inductor values result in higher ripple current which causes the transition to occur at lower load currents. this causes a dip in effciency in the upper range of low current operation. furthermore, lower inductance values will cause the bursts to occur with increased frequency. inductor core selection different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style induc- tor to use often depends more on the price versus size requirements, and any radiated feld/emi requirements, than on what the ltc3619b requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3619b applications. table 1. representative surface mount inductors manu- facturer part number value max dc current dcr height coilcraft lps4012-152ml lps4012-222ml lps4012-332ml lps4012-472ml lps4018-222ml lps4018-332ml lps4018-472ml 1.5h 2.2h 3.3h 4.7h 2.2h 3.3h 4.7h 2200ma 1750ma 1450ma 1450ma 2300ma 2000ma 1800ma 0.070 0.100 0.100 0.170 0.070 0.080 0.125 1.2mm 1.2mm 1.2mm 1.2mm 1.8mm 1.8mm 1.8mm fdk fdkmipf2520d fdkmipf2520d fdkmipf2520d 4.7h 3.3h 2.2h 1100ma 1200ma 1300ma 0.11 0.1 0.08 1mm 1mm 1mm murata lqh32cn4r7m23 4.7h 450ma 0.2 2mm panasonic elt5kt4r7m 4.7h 950ma 0.2 1.2mm sumida cdrh2d18/ld cdh38d11snp- 3r3m cdh38d11snp- 2r2m 4.7h 3.3h 2.2h 630ma 1560ma 1900ma 0.086 0.115 0.082 2mm 1.2mm 1.2mm taiyo yuden cb2016t2r2m cb2012t2r2m cb2016t3r3m nr30102r2m nr30104r7m 2.2h 2.2h 3.3h 2.2h 4.7h 510ma 530ma 410ma 1100ma 750ma 0.13 0.33 0.27 0.1 0.19 1.6mm 1.25mm 1.6mm 1mm 1mm tdk vlf3010at4r7- mr70 vlf3010at3r3- mr87 vlf3010at2r2- m1r0 vlf4012at-2r2 m1r5 vlf5012st-3r3 m1r7 vlf5014st-2r2 m2r3 4.7h 3.3h 2.2h 2.2h 3.3h 2.2h 700ma 870ma 1000ma 1500ma 1700ma 2300ma 0.28 0.17 0.12 0.076 0.095 0.059 1mm 1mm 1mm 1.2mm 1.2mm 1.4mm v in run2 run1 ltc3619b v fb2 sw2 sw1 pgood1 pgood2 v fb1 c f2 c f1 gnd v in 2.5v to 5.5v v out2 v out1 3619b f02 r4 r2 r3 r1 l2 l1 c out2 c out1 c1 r lim c lim rlim figure 2. ltc3619b general schematic a pplica t ions i n f or m a t ion
ltc3619b 3619bfa a pplica t ions i n f or m a t ion input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out / v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms i max v out (v in ? v out ) v in where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling when not using an all-ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. the output ripple v out is determined by: v out i l esr + 1 8f o c out ? ? ? ? ? ? where f o = operating frequency, c out = output capacitance and i l = ripple current in the inductor. for a fxed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. if tantalum capacitors are used, it is critical that the capaci- tors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum. these are specially constructed and tested for low esr so they give the lowest esr for a given volume. other capacitor types include sanyo poscap, kemet t510 and t495 series, and sprague 593d and 595d series. consult the manufacturer for other specifc recommendations. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. because the ltc3619b control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. however, care must be taken when ceramic capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in , large enough to damage the part. for more information, see application note 88. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. setting the output voltage the ltc3619b regulates the v fb1 and v fb2 pins to 0.6v dur- ing regulation. thus, the output voltage is set by a resistive divider, figure 2, according to the following formula: v out = 0.6v 1 + r2 r1 ? ? ? ? ? ? (2) keeping the current small (< 10a) in these resistors maximizes effciency, but making it too small may allow stray capacitance to cause noise problems or reduce the phase margin of the error amp loop. to improve the frequency response of the main control loop, a feedback capacitor (c f ) may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line.
ltc3619b 3619bfa a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine the phase margin. in addition, feedback capacitors (c f1 and c f2 ) can be added to improve the high frequency response, as shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a re- view of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in paral- lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifcally for this purpose and usually incorporates cur- rent limiting, short-circuit protection, and soft-starting. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: % effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four sources usually account for the losses in ltc3619b circuits: 1) v in quiescent current, 2) switching losses, 3) i 2 r losses, 4) other system losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2. the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current fows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top ) ? (dc) + (r ds(on)bot ) ? (1C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 ? (r sw + r l )
ltc3619b 3619bfa a pplica t ions i n f or m a t ion 4. other hidden losses, such as copper trace and internal battery resistances, can account for additional effciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching fre- quency. other losses, including diode conduction losses during dead-time, and inductor core losses, generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3619b does not dis- sipate much heat due to its high effciency. in the unlikely event that the junction temperature somehow reaches ap- proximately 150c, both power switches will be turned off and the sw node will become high impedance. the goal of the following thermal analysis is to determine whether the power dissipated causes enough temperature rise to exceed the maximum junction temperature (125c) of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as a worst-case example, consider the case when the ltc3619b is in dropout on both channels at an input voltage of 2.7v with a load current of 400ma and 800ma and an ambient temperature of 70c. from the typical performance characteristics graph of switch resistance, the r ds(on) of the switch is 0.56 and 0.33. therefore, power dissipated by each channel is: p d1 = i out 2 ? r ds(on) = 90mv p d2 = i out 2 ? r ds(on) = 212mv given that the thermal resistance of a properly soldered dfn package is approximately 40c/w, the junction temperature of an ltc3619b device operating in a 70c ambient temperature is approximately: t j = (0.302w ? 40c/w) + 70c = 82.1c which is well below the absolute maximum junction tem- perature of 125c. pc board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3619b. these items are also illustrated graphically in the layout diagrams of figures 3a and 3b. check the following in your layout: 1. does the capacitor c in connect to the power v in (pin 6) and gnd (pin 11) as closely as possible? this capacitor provides the ac current of the internal power mosfets and their drivers. 2. are the respective c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out1 and a ground sense line terminated near gnd (pin 11). the feedback sig- nals v fb1 and v fb2 should be routed away from noisy components and traces, such as the sw lines (pins 5 and 7), and their trace length should be minimized. 4. keep sensitive components away from the sw pins, if possible. the input capacitor c in , c lim and the resistors r1, r2, r3 and r4 and r lim should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at a single point. these ground traces should not share the high current path of c in or c out . 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to v in or gnd.
ltc3619b 3619bfa figure 3a. ltc3619b layout diagram (see board layout checklist) a pplica t ions i n f or m a t ion v in run2 run1 ltc3619b v fb2 sw2 sw1 v fb1 c f2 c f1 gnd rlim v in 2.5v to 5.5v v out2 v out1 3619b f03a r3 r1 r4 l2 l1 r2 c out2 c1 c out1 bold lines indicate high current paths pgood1 pgood2 r lim c lim figure 3b. ltc3619b suggested layout 3619b f03b v in v in sw2 pgood2 run2 v fb2 sw1 pgd1 rlim run1 v fb1 c in v out1 v out2 c out1 c out2 gnd gnd l2 l1 v in via gnd via via to v out2 via to v out1 r3 r1 r4 r2 c f2 r lim c lim c f1
ltc3619b 3619bfa a pplica t ions i n f or m a t ion design example as a design example, consider using the ltc3619b in a usb-gsm application, with v in = 5v, i inmax = 500ma, with the output of channel 2 charging a supercap of 4.4mf. the load on each channel requires a maximum of 400ma and 800ma in active mode and 2ma in standby mode. the output voltages are v out1 = 1.8v and v out2 = 3.4v. start with channel 1. first, calculate the inductor value for about 40% ripple current (160ma in this example) at maximum v in . using a derivation of equation 1: l1 = 1.8v 2.25mhz ? (160ma) ? 1 ? 1.8v 5v ? ? ? ? ? ? = 3.2h for the inductor, use the closest standard value of 3.3h. a 10f ceramic capacitor should be more than suffcient for this output capacitor. as for the input capacitor, a typical value of c in = 10f should suffce, if the source impedance is very low. the feedback resistors program the output voltage. to maintain high effciency at light loads, the current in these figure 4a. design example circuit resistors should be kept small. choosing 10a with the 0.6v feedback voltage makes r1~60k. a close standard 1% resistor is 59k. using equation 2. r2 = v out 0.6 ? 1 ? ? ? ? ? ? ? r1 = 118k an optional 22pf feedback capacitor (c f1 ) may be used to improve transient response. using the same analysis for channel 2 (v out2 = 3.4v), the results are: l2 = 1.5h r3 = 59k r4 = 276k a feed forward capacitor is not used on channel 2 since the 4.4mf supercap will inhibit any fast output voltage transients. figure 4 shows the complete schematic for this example, along with the effciency curve and transient response. input current limit is set at 475ma average cur- rent, r lim = 116k, c lim = 2200pf. see programming input current limit section for selecting r lim and selection of c lim capacitance section for c lim . v in run2 run1 ltc3619b v fb2 sw2 sw1 pgood1 pgood2 v fb1 c f1 , 22pf gnd rlim v in usb input 5v v out2 3.4v at 800ma v out1 1.8v at 400ma 3619b f04a r4 276k r2 118k r3 59k r1 59k l2 1.5h l1 3.3h c out2 2.2mf s2 supercap c out1 10f c in 10f r lim 116k c lim 2200pf + i lim = 475ma c in , c out1 : avx 08056d106kat2a c out2 : vishay 592d228x96r3x2t20h l1: coilcraft lps4012-332ml l2: coilcraft lps4012-152ml
ltc3619b 3619bfa a pplica t ions i n f or m a t ion figure 4b. effciency vs output current figure 4c. transient response output current (a) efficiency (%) power loss (w) power loss (w) 100 90 80 70 60 50 40 30 20 10 0 10 1 0.1 0.01 0.001 10 1 0.1 0.01 0.001 0.0001 0.1 1 0.01 0.001 v out = 1.8v output current (a) efficiency (%) 3619b f04b 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.1 1 0.01 0.001 v out = 3.4v v in = 3.6v v in = 4.2v v in = 5v v in = 2.7v v in = 3.6v v in = 4.2v v in = 5v 20s/div v in = 5v, v out = 1.8v i load = 40ma to 400ma c l = 10f v out 100mv/div ac-coupled i load 500ma/div i l 500ma/div 1ms/div v in = 5v, 500ma compliant r lim = 116k, c lim = 2200pf i load = 0a to 2a, c out = 4.4mf, v out = 3.4v i lim = 475ma, channel 1 not loaded 3619b f04c v in 1v/div ac-coupled v out 200mv/div i in 500ma/div i out 500ma/div
ltc3619b 3619bfa msop (mse) 0908 rev c 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 p 0.152 (.193 p .006) 0.497 p 0.076 (.0196 p .003) ref 8910 10 1 7 6 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0o ? 6o typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 2.083 p 0.102 (.082 p .004) 2.794 p 0.102 (.110 p .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 p 0.102 (.072 p .004) 2.06 p 0.102 (.081 p .004) 0.1016 p 0.0508 (.004 p .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref p ackage descrip t ion 3.00 p0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.65 p 0.10 (2 sides) 0.75 p0.05 r = 0.125 typ 2.38 p0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev b 0309 0.25 p 0.05 2.38 p0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p0.05 (2 sides) 2.15 p0.05 0.50 bsc 0.70 p0.05 3.55 p0.05 package outline 0.25 p 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm s 3mm) (reference ltc dwg # 05-08-1699 rev b) mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev c)
ltc3619b 3619bfa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/10 changes to temperature range in order information section updates in the electrical characteristics table edit on y-axis on graph g18 updated dd package drawing 2 3 5 18
ltc3619b 0 3619bfa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0410 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ions dual 400ma/800ma buck converter, i lim = 500ma dual 400ma/800ma buck converter, i lim = 475ma or disabled v in run2 run1 ltc3619b v fb2 sw2 sw1 pgood1 pgood2 v fb1 c f1 , 22pf gnd rlim v in 3.3v to 5.5v v out2 3.3v at 800ma v out1 1.8v at 400ma 3619b ta02 r4 1150k r2 511k r3 255k r1 255k l2 1.5h l1 3.3h c out2 2.2mf s2 supercap c out1 10f c1 10f c1, c out1 : avx 08056d106kat2a c out2 : vishay 592d228x96r3x2t20h l1: coilcraft lps4012-332ml l2: coilcraft lps4012-152ml r lim 110k c lim 1000pf + v in run2 run1 ltc3619b v fb2 sw2 sw1 pgood1 pgood2 v fb1 c f1 , 22pf gnd r lim v in 3.3v to 5.5v v out2 3.3v at 800ma v out1 1.8v at 400ma 3619b ta03 r4 1150k r2 511k r3 255k r1 255k l2 1.5h l1 3.3h c out2 2.2mf s2 supercap i lim disable c out1 10f c1 10f r lim 116k c lim 2200pf + c1, c out1 : avx 08056d106kat2a c out2 : vishay 592d228x96r3x2t20h l1: coilcraft lps4012-332ml l2: coilcraft lps4012-152ml part number description comments ltc3619 dual 400ma and 800ma i out , 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 50a, i sd < 1a, ms10e, 3mm 3mm dfn-10 ltc3127 1.2a i out , 1.6mhz, synchronous buck-boost dc/dc converter with adjustable input current limit 94% effciency, v in(min) = 1.8v, v in(max) = 5.5v, v out(max) = 5.25v, i q = 18a, i sd < 1a, 3mm 3mm dfn-msop10e ltc3125 1.2a i out , 1.6mhz, synchronous boost dc/dc converter with adjustable input current limit 94% effciency, v in(min) = 1.8v, v in(max) = 5.5v, v out(max) = 5.25v, i q = 15a, i sd < 1a, 2mm 3mm dfn-8 ltc3417a/ ltc3417a-2 dual 1.5a/1a, 4mhz, synchronous step-down dc/dc converter 95% effciency, v in(min) = 2.3v, v in(max) = 5.5v, v out(min) = 0.8v, i q = 125a, i sd = <1a, tssop-16e, 3mm 5mm dfn-16 ltc3407a/ ltc3407a-2 dual 600ma/600ma, 1.5mhz, synchronous step-down dc/dc converter 95% effciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 40a, i sd = <1a, ms10e, 3mm 3mm dfn-10 ltc3548/ltc3548-1/ ltc3548-2 dual 400ma and 800ma i out , 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in(min) = 2.5v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 40a, i sd = <1a, ms10e, 3mm 3mm dfn-10 ltc3546 dual 3a/1a, 4mhz, synchronous step-down dc/dc converter 95% effciency, v in(min) = 2.3v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 160a, i sd = <1a, 4mm 5mm qfn-28

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